1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to an operation test performed in a semiconductor integrated circuit device including a plurality of circuit blocks having the same function.
2. Description of the Background Art
Following the recent development of the circuit integration technique, the development of semiconductor integrated circuit devices, represented by LSI (Large Scale Integrated Circuit), including a plurality of circuit blocks is underway. Before shipping these semiconductor integrated circuit devices, it is necessary to select non-defective and defective devices by performing operation tests. However, as the semiconductor integrated circuit devices are made larger in size, demand for efficiently executing such operation tests at low cost rises. Specifically, it is demanded to prevent the cost hike of an LSI tester used to executed each operation test and to reduce operation test time.
FIG. 6 is a block diagram for describing the configuration of an operation test performed to a conventional semiconductor integrated circuit device.
Referring to FIG. 6, a conventional semiconductor integrated circuit device 200 includes a plurality of circuit blocks CB(1), CB(2), . . . , and CB(m). Each of circuit blocks CB(1), CB(2), . . . , and CB(m) consists of a plurality of logic circuits (m is natural number). For example, circuit block CB(1) consists of logic circuits LG1a, LG1b and LG1c. Circuit block CB(2) consists of logic circuits LG2a, LG2b and LG2c. Circuit block CB(m) consists of logic circuits LGma, LGmb and LGmc. These logic circuits will be also, typically referred to as “logic circuit LG” hereinafter.
Data input terminals IT(1) to IT(m) and data output terminals OT(1) to OT(m) are provided to correspond to circuit blocks CB(1) to CB(m), respectively. In normal operation, pieces of input data inputted into data input terminals IT(1) to IT(m) are sequentially subjected to predetermined logic operations by corresponding logic circuits LG, and pieces of obtained output data are outputted from corresponding data output terminals OT(1) to OT(m), respectively.
Each of logic circuits LG operates in response to a system clock which is not shown. The system clock is supplied from the outside of semiconductor integrated circuit device 200 in the normal operation. Alternatively, the system clock can be automatically generated in semiconductor integrated circuit device 200. In an operation test, the system clock is applied from an LSI tester 300, which tests the operation of semiconductor integrated circuit 200, to respective logic circuits LG.
Further, in order to execute operation tests to these circuit blocks, scan input terminals SIT(1) to SIT(m) and scan output terminals SOT(1) to SOT(m) are arranged to correspond to circuit blocks CB(1) to CB(m), respectively.
In the operation test, test pattern data TPD(1) to TPD(m) used in the operation tests to circuit blocks CB(1) to CB(m) are inputted into scan input terminals SIT(1) to SIT(m), respectively.
Test pattern data TPD(1) to TPD(m) are generated by LSI tester 300. LSI tester 300 includes a test pattern generation tool 310, a test pattern memory 320, an expected value memory 330, and an expected value evaluation tool 340.
Test pattern generation tool 310 automatically generates test pattern data TPD(1) to TPD(m) used for executing operation tests in circuit blocks CB(1) to CB(m), respectively, on the basis of preset test patterns. Test pattern data TPD(1) to TPD(m) generated by test pattern generation tool 310 are temporarily stored in test pattern memory 320, and inputted into circuit blocks CB(1) to CB(m) through scan input terminals SIT(1) to SIT(m), respectively.
Test pattern generation tool 310 also generates a group of expected value data EXD corresponding to test pattern data TPD(1) to TPD(m), respectively. Expected value data group EXD is transmitted to and stored in expected value memory 330. Expected value data group EXD stored in expected value memory 330 is transmitted to expected value evaluation tool 340 if necessary.
An operation test executed in each circuit block will next be described, taking an operation test in circuit block CB(1) as an example.
Test pattern data TPD(1) inputted into scan input terminal SIT(1) is transmitted to a leading scan cell SC. In an operation test, a scan clock (not shown) is inputted into respective scan cells SC from LSI tester 300. Scan cell SC consecutively shifts the test pattern data applied thereto, to next scan cell SC in response to the scan clock. For example, leading scan cell SC captures data inputted into scan input terminal SIT(1) and transmits the data which has been held therein so far to next scan cell SC in response to the scan clock. The supply of the scan clock from LSI tester 300 is continuously executed until test pattern data TPD(1) is transmitted to all corresponding scan cells SC in accordance with a predetermined test pattern.
When the setting of the test pattern data to scan cells SC is completed, the system clock is supplied to respective logic circuits LG from LSI tester 300. In response to the supply of the system clock, each logic circuit LG executes a predetermined logic operation and executes an operation processing based on the data inputted into corresponding scan cells SC. At a timing at which the operation test target logic circuits complete their operation processings, LSI tester 300 stops supplying the system clock thereto. At this stage, output data which is an operation processing result corresponding to test pattern data TPD(1) in each logic circuit LG has been outputted to corresponding scan cells SC.
LSI tester 300 restarts supplying the scan clock to respective scan cells SC so as to output the output data from scan output terminal SOUT(1). In response to the restart of the supply of the scan clock, pieces of output data from logic circuits LG1a, LG1b and LG1c which constitutes circuit block CB(1), are sequentially outputted from scan output terminal SOUT(1) as pieces of test output data TDO(1).
As can be seen, the pieces of test output data TDO(1) which have been sequentially outputted are transmitted to expected value evaluation tool 340 in LSI tester 300. Expected value evaluation tool 340 compares the expected value among expected value data group EXD stored in expected value memory 330 in advance, corresponding to the pieces of test output data TDO(1), with the pieces of test output data TDO(1), respectively, and thereby evaluates whether the operation of circuit block CB(1) is normal, i.e., whether there is a failure in circuit block CB(1).
The same operation test as that performed to circuit block CB(1) can be executed to each of other circuit blocks CB(2) to CB(m). Therefore, it is possible to execute operation tests in respective circuit blocks CB(1) to CB(m) in parallel and to complete the operation tests to the plurality of circuit blocks in short time.
Recently, a plurality of circuit blocks each having the same circuit configuration and the same function are mounted on the same semiconductor integrated circuit device quite frequently. This corresponds to a case, for example, in which each of circuit blocks CB(1) to CB(m) shown in FIG. 6 has the same function and the same circuit configuration.
However, with the configuration of the conventional semiconductor integrated circuit device shown in FIG. 6, pieces of test pattern data TPD(1) to TPD(m) are inputted into the respective circuit blocks independently of one another. Due to this, operation tests can be advantageously executed to a plurality of circuit blocks in parallel even if they differ in function. On the other hand, if each of the circuit blocks has the same circuit configuration, operation tests becomes disadvantageously inefficient.
That is, even if each of circuit blocks CB(1) to CB(m) has the same circuit configuration and an operation test can be executed in response to the input of common test pattern data, it is required to separately generate test pattern data TPD(1) to TPD(m) to correspond to the m circuit blocks, respectively. As a result, test pattern memory 320 and expected value memory 330 included in LSI tester 300 become disadvantageously large in size.
Consequently, in order to perform an operation test to a semiconductor integrated circuit device which includes a plurality of circuit blocks each having the same function, it is necessary to employ a relatively expensive LSI tester which includes a mass storage test pattern memory and a mass storage expected value memory. In addition, the operation time of test pattern generation tool 310 which generates the test pattern data and the expected value group is lengthened, thereby disadvantageously deteriorating the efficiency of the operation test.